PD0_SLEEP0_HW_ENA

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Interpret as PD0_SLEEP0_HW_ENA

Hardware sleep event enable register

ENA_EVENT0	Writing a 1 enables the Cortex-M3 core to put the part into any of the Power-down modes Deep-sleep, Power-down, or Deep power-down depending on the value in the PD0_SLEEP0_MODE register
RESERVED	Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

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